1. Field of the Invention
The invention relates to a driver circuit for binary signals. The invention relates to a driver circuit for binary signals, said circuit having two parallel driver branches. A preferred, but not exclusive, area of application of the invention is the amplification of binary data signals and/or control signals at the outputs of digital modules, particularly at the outputs of DRAM memory circuits and associated memory controllers.
2. Description of the Related Art
A driver circuit for amplifying binary signals which represent serial bits of an item of information usually contains controllable switching elements which are driven by the binary signal to be amplified in order to connect an output node either to a first or to a second defined logic potential depending on the binary state of this signal. The controllable switching elements may be two on/off switches, preferably two field effect transistors (FETs) of a complementary conduction type (one P-FET and one N-FET), which are driven by the binary signal to be amplified via separate branches and which form the output stages of the branches. If the driving binary signal has the first binary value (e.g. “1”), only the first switch (e.g. the P-FET) is on in order to pull the output node to the first logic potential (e.g. the more positive potential “H”). If the driving binary signal has the second binary value (e.g. “0”), only the second switch (e.g. the N-FET) is on in order to pull the output node to the second logic potential (e.g. the more negative potential “L”). During the transition from one binary value to the other, the conductivity of the two switches changes in the opposite sense, both switches temporarily being on to a greater or lesser extent. In many cases, suitable preamplifiers are respectively connected upstream of the output stages of the two driver branches.
In particular, if driver circuits of the above-described type are used as output amplifiers of a module in order to transmit the amplified signals to a load (receiver) via a line, the connection (which is established by means of the switching elements) of the output node to the respective logic potential is effected via a respective nonreactive resistor. These resistors are referred to as “pull-up” or “pull-down” resistors depending on whether they lead to the H potential or to the L potential. The termination of such driver circuits, that is to say the termination of the line at the load or receiver end, is then likewise effected resistively, either “asymmetrically”, that is to say at only one of the logic potentials via one terminating resistor, or “symmetrically”, that is to say at the H potential and the L potential via two terminating resistors. The pull-up, pull-down and terminating resistors are dimensioned, taking into account the effective characteristic impedance of the line, in such a manner that there is no reflection as far as possible.
Inevitable process fluctuations when manufacturing the driver circuit may result in the form and the timing of the edges when passing through the driver circuit not only being influenced differently from circuit to circuit but also in this influence being different for edges of differing polarity. By way of example, the threshold point (switching threshold) and the slope of the characteristic curves of the switching elements in the output stages of the two branches may thus differ from one another. One consequence of this asymmetry may be that the edges of one polarity (e.g. the “rising” edges which are changing to the H potential) of the output signal are “slower”, i.e. last longer or are delayed to a greater extent, than the edges of the other polarity (e.g. the “falling” edges which are changing to the L potential). Time displacement differences between rising and falling edges in the output signal may also arise if preamplifiers which are inserted into the two driver branches also have asymmetries. All of these effects are of concern, in particular, when the switching elements in the output stages (and also in any possible preamplifiers) are FETs of a complementary conduction type.
These effects lead to “duty ratio distortion” in the output signal; that is to say the amplitude/time integrals of signal excursions of one polarity (which represent the “1” bits, for example) are different than the amplitude/time integrals of the signal excursions of the other polarity (“0” bits). However, the ratio of these integrals should, on average, be equal to 1. Otherwise an undesirable offset occurs in the reception of the signals at the load, said offset additionally fluctuating depending on the composition of the bit sequence.